1. Field of the Invention
The present invention relates to a data driver, and more particularly, to a data driver included in a current driving (or writing) type organic light emitting display device and a method of driving the same.
2. Discussion of Related Art
An active matrix organic light emitting display (AMOLED) device can be either a voltage driving (or writing) type organic light emitting display device using a voltage writing method to write a voltage signal in a panel to display a desired image on the panel or a current driving (or writing) type organic light emitting display device using a current writing method to write a current signal in a panel to display a desired image on the panel.
In the voltage writing method, a data driving integrated circuit used for driving a liquid crystal display (LCD) can be used. However, since poly-Si thin film transistors (TFTs) used for manufacturing the AMOLED device have large deviations in threshold voltages and/or mobility, the AMOLED device using the voltage writing method has a problem in providing uniform picture quality.
By contrast, the AMOLED device using the current writing method can concurrently compensate for process deviations in the threshold voltages and mobility of the poly-Si TFTs. However, in order to drive the AMOLED panel using the current writing method, a constant current output data driving integrated circuit is required. Here, the constant output data driving integrated circuit needs to provide output currents having a deviation small enough to make picture quality uniform and also needs to be capable of fully driving the parasitic resistance and parasitic capacitance load of the data lines of the panel.
FIG. 1 is a block diagram illustrating a conventional data driver used for the AMOLED device using the current writing method.
Referring to FIG. 1, the conventional data driver used for the AMOLED device using the current writing method includes a shift register 10, a sampling latch 20, a holding latch 30, a digital-to-analog converter 40, and a current output stage 50.
The shift register 10 sequentially shifts start signals IE in accordance with input clock signals CLK and generates sampling signals to supply the sampling signals to the sampling latch 20. The shift register 10 is composed of registers (for example, D flip-flops) whose number is equal to the number of output channels of the current output stage 50. Also, the shift register 10 can output the sampling signals in both directions (from left to right and from right to left) in accordance with shift direction signals SHL for determining shift directions.
The sampling latch 20 latches digital data (R, G, and B data) applied from the outside to data bus lines in accordance with the sampling signals sequentially supplied from the shift register 10 in response to the start signals IE to store the digital data. The sampling latch 20 is composed of registers (for example, D flip-flops) whose number is equal to the number of output channels of the shift register 10.
The holding latch 30 receives the digital data (R, G, and B data) latched by the sampling latch 20 in accordance with holding start signals DH supplied from the outside to hold the latched digital data (R, G, and B data) for one horizontal line period (or row-line time). The holding latch 30 is composed of registers (for example, D flip-flops) whose number is equal to the number of output channels of the sampling latch 20.
The digital-to-analog converter 40 generates the currents corresponding to the digital data (R, G, and B data) supplied from the holding latch 30 using the currents supplied from a current source (not shown). The digital-to-analog converter 40 supplies the generated currents to the current output stage 50 in accordance with input clock signals SCLK.
The current output stage 50 sequentially samples the currents supplied from the digital-to-analog converter 40 to output the sampled currents.
That is, the conventional data driver used for the AMOLED device using the current writing method generates the currents corresponding to the digital data (R, G, and B data) supplied from the outside to output the currents to the outside through output channels Co1 to Con.
FIG. 2 is a block diagram schematically illustrating an example of the digital-to-analog converter 40 illustrated in FIG. 1.
Referring to FIGS. 1 and 2, the digital-to-analog converter 40 includes a decoder 42 and a digital-to-analog conversion (DAC) core 44.
The decoder 42 decodes the held digital data (R, G, and B data) supplied from the holding latch 30 to supply the decoded digital data (R, G, and B data) to the DAC core 44.
The DAC core 44 generates the currents IDAC corresponding to the decoded digital data (R, G, and B data) supplied from the decoder 42 to supply the currents IDAC to the current output stage 50. Therefore, the DAC core 44 includes a current source array (not shown) for generating the currents IDAC corresponding to the decoded digital data (R, G, and B data) supplied from the decoder 42 and a DAC bias circuit for supplying reference current to the current source array. The DAC core 44 generates the currents IDAC corresponding to the digital data (R, G, and B data) supplied from the decoder 42 using the reference current generated by the current source array to output the generated currents IDAC to the current output stage 50 in synchronization with the clock signals SCLK supplied from the outside.
In a process of the above conventional data driver where the digital data (R, G, and B data) held by the holding latch 30 are supplied to the decoder 42 of the digital-to-analog converter 40, the characteristics of the output currents IDAC of the digital-to-analog converter 40 deteriorate due to the parasitic resistance and the parasitic capacitance in the digital-to-analog converter 40 and/or the difference in the characteristics of the threshold voltages of transistors of the data driver.